module clock_divider(
    input clk_in,
    input reset,
    output clk_out
);
    reg [31:0] counter;
    reg divided_clk;
    always @(posedge clk_in or posedge reset) begin
        if (reset) begin
            counter <= 32'd0;
            divided_clk <= 1'b0;
        end else begin
            if (counter == 32'd49_999_999) begin
                counter <= 32'd0;
                divided_clk <= ~divided_clk;
            end else begin
                counter <= counter + 1;
            end
        end
    end
    assign clk_out = divided_clk;
endmodule
